Commit ccb9af21 authored by Jens Dieskau's avatar Jens Dieskau
Browse files

Update device tree data

parent 83783441
......@@ -37,7 +37,7 @@ DTB_LIST := $(addsuffix .dtb,$(DTB_NAMES))
else
DTB_LIST := $(dtb-y)
endif
DTB_OBJS := $(addprefix $(obj)/dts/,$(DTB_LIST))
DTB_OBJS := $(addprefix $(obj)/dts/qcom/,$(DTB_LIST))
ifeq ($(CONFIG_XIP_KERNEL),y)
......
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/*
* Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
*
* Licensed under the X11 license or the GPL v2 (or later)
*/
/dts-v1/;
#include "alphascale-asm9260.dtsi"
/ {
model = "Alphascale asm9260 Development Kit";
compatible = "alphascale,asm9260devkit", "alphascale,asm9260";
};
/*
* Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
*
* Licensed under the X11 license or the GPL v2 (or later)
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/alphascale,asm9260.h>
/ {
interrupt-parent = <&icoll>;
memory {
device_type = "memory";
reg = <0x20000000 0x2000000>;
};
cpus {
#address-cells = <0>;
#size-cells = <0>;
cpu {
compatible = "arm,arm926ej-s";
device_type = "cpu";
clocks = <&acc CLKID_SYS_CPU>;
};
};
osc24m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-accuracy = <30000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
acc: clock-controller@80040000 {
compatible = "alphascale,asm9260-clock-controller";
#clock-cells = <1>;
clocks = <&osc24m>;
reg = <0x80040000 0x204>;
};
icoll: interrupt-controller@80054000 {
compatible = "alphascale,asm9260-icoll";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x80054000 0x200>;
};
timer0: timer@80088000 {
compatible = "alphascale,asm9260-timer";
reg = <0x80088000 0x4000>;
clocks = <&acc CLKID_AHB_TIMER0>;
interrupts = <29>;
};
};
};
/*
* Copyright 2015 Annapurna Labs Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* Alternatively, redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
/dts-v1/;
#include "alpine.dtsi"
/ {
model = "Annapurna Labs Alpine Dev Board";
/* no need for anything outside SOC */
};
/*
* Copyright 2015 Annapurna Labs Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* Alternatively, redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton64.dtsi"
/ {
/* SOC compatibility */
compatible = "al,alpine";
/* CPU Configuration */
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "al,alpine-smp";
cpu@0 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <0>;
clock-frequency = <0>; /* Filled by loader */
};
cpu@1 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <1>;
clock-frequency = <0>; /* Filled by loader */
};
cpu@2 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <2>;
clock-frequency = <0>; /* Filled by loader */
};
cpu@3 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <3>;
clock-frequency = <0>; /* Filled by loader */
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
arch-timer {
compatible = "arm,cortex-a15-timer",
"arm,armv7-timer";
interrupts =
<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <0>; /* Filled by loader */
};
/* Interrupt Controller */
gic: gic@fb001000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
#size-cells = <0>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xfb001000 0x0 0x1000>,
<0x0 0xfb002000 0x0 0x2000>,
<0x0 0xfb004000 0x0 0x1000>,
<0x0 0xfb006000 0x0 0x2000>;
interrupts =
<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
/* CPU Resume registers */
cpu-resume@fbff5ec0 {
compatible = "al,alpine-cpu-resume";
reg = <0x0 0xfbff5ec0 0x0 0x30>;
};
/* North Bridge Service Registers */
sysfabric-service@fb070000 {
compatible = "al,alpine-sysfabric-service", "syscon";
reg = <0x0 0xfb070000 0x0 0x10000>;
};
/* Performance Monitor Unit */
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
uart0:uart@fd883000 {
compatible = "ns16550a";
reg = <0x0 0xfd883000 0x0 0x1000>;
clock-frequency = <0>; /* Filled by loader */
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart1:uart@0xfd884000 {
compatible = "ns16550a";
reg = <0x0 0xfd884000 0x0 0x1000>;
clock-frequency = <0>; /* Filled by loader */
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
/* Internal PCIe Controller */
pcie-internal@0xfbc00000 {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
#interrupt-cells = <1>;
reg = <0x0 0xfbc00000 0x0 0x100000>;
interrupt-map-mask = <0xf800 0 0 7>;
/* Add legacy interrupts for SATA devices only */
interrupt-map = <0x4000 0 0 1 &gic 0 43 4>,
<0x4800 0 0 1 &gic 0 44 4>;
/* 32 bit non prefetchable memory space */
ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
bus-range = <0x00 0x00>;
};
};
};
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* VScom OnRISC
* http://www.vscom.de
*/
/dts-v1/;
#include "am33xx.dtsi"
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "OnRISC Baltos iR 5221";
compatible = "vscom,onrisc", "ti,am33xx";
cpus {
cpu@0 {
cpu0-supply = <&vdd1_reg>;
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
vbat: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
wl12xx_vmmc: fixedregulator@2 {
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_gpio>;
compatible = "regulator-fixed";
regulator-name = "vwl1271";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 8 0>;
startup-delay-us = <70000>;
enable-active-high;
};
};
&am33xx_pinmux {
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
0x020 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */
0x024 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */
0x028 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */
0x02c (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */
0x080 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */
0x084 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */
0x1e4 (PIN_INPUT_PULLUP | MUX_MODE7) /* emu0.gpio3[7] */
>;
};
wl12xx_gpio: pinmux_wl12xx_gpio {
pinctrl-single,pins = <
0x1e8 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
>;
};
tps65910_pins: pinmux_tps65910_pins {
pinctrl-single,pins = <
0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */
>;
};
tca6416_pins: pinmux_tca6416_pins {
pinctrl-single,pins = <
0x1b4 (PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x158 0x2a /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */
0x15c 0x2a /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */
>;
};
dcan1_pins: pinmux_dcan1_pins {
pinctrl-single,pins = <
0x168 0x0a /* uart0_ctsn.dcan1_tx_mux0, OUTPUT | MODE2 */
0x16c 0x2a /* uart0_rtsn.dcan1_rx_mux0, INPUT | MODE2 */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
0x180 0x28 /* uart1_rxd, INPUT | MODE0 */
0x184 0x28 /* uart1_txd, INPUT | MODE0 */
/*0x178 0x28*/ /* uart1_ctsn, INPUT | MODE0 */
/*0x17c 0x08*/ /* uart1_rtsn, OUTPUT | MODE0 */
0x178 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn, INPUT | MODE0 */
0x17c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn, OUTPUT | MODE0 */
0x0e0 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */
0x0e4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */
0x0e8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */
0x0ec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
0x150 0x29 /* spi0_sclk.uart2_rxd_mux3, INPUT | MODE1 */
0x154 0x09 /* spi0_d0.uart2_txd_mux3, OUTPUT | MODE1 */
/*0x188 0x2a*/ /* i2c0_sda.uart2_ctsn_mux0, INPUT | MODE2 */
/*0x18c 0x2a*/ /* i2c0_scl.uart2_rtsn_mux0, INPUT | MODE2 */
0x188 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* i2c0_sda.uart2_ctsn_mux0 */
0x18c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* i2c0_scl.uart2_rtsn_mux0 */
0x030 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */
0x034 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */
0x038 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */
0x03c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */
0x1a0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
/* Slave 2 */
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
/* Slave 2 reset value*/
0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
nandflash_pins_s0: nandflash_pins_s0 {
pinctrl-single,pins = <
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
};
&elm {
status = "okay";
};
&gpmc {
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins_s0>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
status = "okay";
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
ti,nand-xfer-type = "polled";
gpmc,device-nand = "true";
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
#address-cells = <1>;
#size-cells = <1>;
elm_id = <&elm>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;